Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects

The tests of a complex system such as a microprocessor-based system-onchip (SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis, we propose three core-based test methods that reuse the existing functional interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC), and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism (TAM). However, the use of functional interconnects as functional TAM's introduces several new problems. During tests, the interconnects-including the bus arbitrator, the bus bridges, and the NoC routers-operate in the functional mode to transport the test stimuli and responses, while the core under tests (CUT) operate in the test mode. Second, the test data is transported to the CUT through the functional bus, and not directly to the test port. Therefore, special core test wrappers that can provide the necessary control signals required by the different functional interconnect are proposed. We developed two types of wrappers, one buffer-based wrapper for the bus-based systems and another pair of complementary wrappers for the NoCbased systems. Using the core test wrappers, we propose test scheduling schemes for the three functionally different types of interconnects. The test scheduling scheme for a flat bus is developed based on an efficient packet scheduling scheme that minimizes both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of the MPSoC systems. The third test scheduling scheme based on the bandwidth sharing is developed specifically for the NoC-based systems. The test scheduling is performed under the objective of co-optimizing the wrapper area cost and the resulting test application time using the two complementary NoC wrappers. For each of the proposed methodology for the three types of SoC architec .. ture, we conducted a thorough experimental evaluation in order to verify their effectiveness compared to other methods

Bio-Inspired Solutions and Its Impact on Real-World Problems: A Network on Chip (NoC) Perspective

Bio-inspired solutions are used to solve the real-world problems as they are able to resolve the complex issues. Already existing bio-inspired solutions are reviewed in this chapter which solved the complex engineering problems. Moreover, this chapter also discusses the implementation of biological brain mechanism in Network on Chip to address the fault-tolerant issues. Network on Chip (NoC) is a communication framework for System on Chip (SoC). Due to routers and interconnect failure, NoC suffers from faults. Therefore, bio-inspired solutions help us to recover from these faults. The techniques from the biological brain were implemented in NoC as the brain is fault tolerant and highly adaptive. Results showed that bio-inspired techniques are performing well compared to the traditional fault-tolerant algorithms

キノウ バス ト NoC インター コネクト オ リヨウシタ システム オンチップ ノ コアベース テスト ニ カンスル ケンキュウ

博士(Doctor)工学(Engineering)奈良先端科学技術大学院大学博第796号甲第796号博士(工学)奈良先端科学技術大学院大

A multi-voltage aware resistive open fault model

Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.The presented model is expected to substantially enhance multi-voltage test generation and fault distinctio

Localization of optic disc and fovea in retinal images using intensity based line scanning analysis

International audienceAccurate detection of diabetic retinopathy (DR) mainly depends on identification of retinal landmarks such as optic disc and fovea. Present methods suffer from challenges like less accuracy and high computational complexity. To address this issue, this paper presents a novel approach for fast and accurate localization of optic disc (OD) and fovea using one-dimensional scanned intensity profile analysis. The proposed method utilizes both time and frequency domain information effectively for localization of OD. The final OD center is located using signal peak-valley detection in time domain and discontinuity detection in frequency domain analysis. However, with the help of detected OD location, the fovea center is located using signal valley analysis. Experiments were conducted on MESSIDOR dataset, where OD was successfully located in 1197 out of 1200 images (99.75%) and fovea in 1196 out of 1200 images (99.66%) with an average computation time of 0.52 s. The large scale evaluation has been carried out extensively on nine publicly available databases. The proposed method is highly efficient in terms of quickly and accurately localizing OD and fovea structure together compared with the other state-of-the-art methods

Advances in Testing Techniques for Digital Microfluidic Biochips

With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips